1. Technical Field of the Invention
The invention relates generally to devices that include a hard disk drive (HDD); and, more particularly, it relates to management of the various functions that are performed within such devices that include a HDD.
2. Description of Related Art
As is known, many varieties of memory storage devices (e.g., disk drives/HDDs), such as magnetic disk drives are used to provide data storage for a host device, either directly, or through a network such as a storage area network (SAN) or network attached storage (NAS). Typical host devices include stand alone computer systems such as a desktop or laptop computer, enterprise storage devices such as servers, storage arrays such as a redundant array of independent disks (RAID) arrays, storage routers, storage switches and storage directors, and other consumer devices such as video game systems and digital video recorders. These devices provide high storage capacity in a cost effective manner.
Within prior art HDD systems, there are several systems that operate simultaneously and require the allocation of a certain degree of processing resources. In prior art HDD systems, a singular processor is typically provisioned in an effort to service these various systems. More specifically, prior art HDD controllers rely on a main processor to do multiple hard real-time control functions. In prior art HDD systems, either the performance of the overall system suffered or the firmware complexity is greatly increased in these prior art implementations that seek to perform all of these functions using the single processor.
There is a deficiency in the prior art, in that, the current means of servicing the various functionality required within a device that includes a HDD generally requires an inordinate amount of involvement by a main/single processor that is implemented to perform a wide variety of functions, many of which are consumptive of a majority the main processor's capability and processing resources.
FIG. 5 illustrates a prior art embodiment of an apparatus 500 that employs a single processor to service multiple control loops. The apparatus 500 includes a prior art HDD controller integrated circuit (IC) 560. The host interface 502 is controlled with a host manager module 570 that is operable to move data between the host interface 502 and a buffer (typically external to the HDD controller IC 560) through the buffer manager module 567. The channel 531 of the HDD communicates with the preamp interface 501. The disk manager module 512 controls the channel 531 and moves data between the channel 531 and the buffer through the buffer manager module 567. The buffer manager module 567 arbitrates access to the shared buffer implemented in the DRAM (typically external to the HDD controller IC 560).
Within this prior art apparatus 500, all firmware executes on a single processor 562, which controls the host manager module 570 and disk manager module 512. Cached firmware for the processor 562 may be stored in the DRAM and be accessed through the buffer manager module 567.
The disk manager module 512 typically has a small writable control store to implement a programmable state machine for control of the hardware within the disk manager module 512 and the channel interface (e.g., the channel 531 and the preamp interface 501). Depending on the complexity of the host interface 502, the host manager 570 may have state machines or have a small writable control store to perform its real-time control functions. The processor 562 loads appropriate micro-programs into the control store(s) depending on the desired modes of operation.
As can be seen when considering this embodiment, there are many functions which must be performed within such a HDD controller IC 560. By requiring all of these functions to be supported by the processor 562, certain of the functions will be short-changed with respect to processing capability at certain times. For example, the processor 562 certainly needs to support more than one function in this embodiment, and when a majority (or all) of the processing resources and capabilities of the processor 562 are being used for one of the functions, then other of the functions are not going to be serviced well. In real time applications, this manner of provisioning the processing resources to a single processor 562 can result in significantly reduced performance.